a) Field of the Invention
The present invention relates to an image pickup apparatus for supplying computer equipment with image information.
b) Description of the Related Art
FIG. 1 is a block diagram showing the structure of an image pickup apparatus having a frame transfer type CCD solid state image pickup device. FIG. 2 is a timing chart illustrating the operation of the same image pickup apparatus.
A CCD solid state image pickup device 1 has an image pickup portion 1i, a storage portion 1s, a horizontal transfer portion 1h and an output portion 1f. The image pickup portion 1i comprises a plurality of vertical shift registers which are arranged parallel to one another. Respective bits of these vertical shift registers form optical pixels. Such multiple optical pixels of the image pickup portion 1i are arranged in the form of a matrix, and information charges are produced on the respective pixels corresponding to the image of an object and independently accumulated in the respective pixels. The storage portion 1s comprises a plurality of vertical shift registers, which are connected to the respective vertical shift registers configuring the image pickup portion 1i. The number of bits of the respective vertical shift registers of the storage portion 1s is set to conform to the number of bits of the vertical shift registers of the image pickup portion 1i. The storage portion 1s can temporarily store information charges for a single image plane being transferred from the vertical shift registers of the image pickup portion 1i. The horizontal transfer portion 1h comprises a single horizontal shift register. The respective outputs of the multiple vertical shift registers of the storage portion is are connected to the respective bits of the horizontal shift register. The horizontal shift register sequentially receives information charges which are transferred in one bit units from the multiple vertical shift registers of the storage portion is and transfers them on a line-by-line basis to the output portion 1f. The output portion If comprises an electrically independent capacitor and an amplifier, which detects a potential change in the capacitor. The information charges transferred from the horizontal shift register of the horizontal transfer portion 1h are received on a pixel-by-pixel basis by the capacitor, and converted into a voltage value. A change in the voltage value is output as an image signal Y0(t).
A vertical drive circuit 2v produces a polyphase vertical transfer clock xcfx86v in response to a vertical timing signal VT and supplies it to the image pickup portion 1i of the solid state image device 1. The information charges for a single image plane, which are produced and stored on each optical pixel of the image pickup portion 1i, are synchronized with the vertical timing signal VT and transferred from the image pickup portion 1i to the storage portion 1s at high speed. The vertical drive circuit 2v produces a polyphase storage clock xcfx86s in response to a horizontal timing signal HT and supplies it to the storage portion 1s. The information charges for a single image plane stored in the storage potion 1s are transferred on a line-by-line basis to the horizontal transfer portion 1h at every cycle of the horizontal timing signal HT. The storage clock xcfx86s also includes a high-speed clock pulse synchronized with the vertical transfer clock xcfx86v for transferring the information charges, which are transferred from the image pickup portion 1i at high speed, into the storage portion 1s. The vertical drive circuit 2v supplies a drain region with a discharge clock xcfx86d, which is started during a vertical scanning period in response to a discharge timing signal DT. The drain region absorbs the electric charges produced excessively in the image pickup portion 1i of the solid state image pickup device 1. The discharge clock xcfx86d controls electric potential in the drain region to discharge the information charges which are stored in the image pickup portion 1i. A period L, during which the information charges are completely discharged by the discharge clock xcfx86d and the information charges are started to be transferred by the vertical clock xcfx86v, is an accumulation time of the information charges (i.e., an image pickup period) in the image pickup portion 1i. The image pickup period of the solid state image pickup device 1, namely a shutter speed, can be controlled according to a change in timing of the discharge clock xcfx86d applied to the substrate. Such methods for discharging information charges are disclosed in, for example, Japanese Patent Laid-Open Publication No. Hei 3-22768 and Japanese Patent Laid-Open Publication No. Hei 3-48586.
A horizontal drive circuit 2h produces a horizontal transfer clock xcfx86h in response to the horizontal timing signal HT and supplies it to the horizontal transfer portion 1h of the solid state image pickup device 1. Accordingly, the information charges, which are transferred on a line-by-line basis from the storage portion is to the horizontal transfer portion 1h, are transferred serially to the output portion 1f. The horizontal drive circuit 2h produces a reset clock xcfx86r synchronized with the horizontal transfer clock xcfx86h and supplies it to the output portion 1f. Thus, information charges stored in the capacitor of the output portion 1f are discharged on a pixel-by-pixel basis. In other words, the quantity of electric charges is converted into the voltage value on a pixel-by-pixel basis.
A horizontal timing control circuit 3h, which includes a counter for counting a base clock BCK with a given cycle, divides the base clock BCK at a predetermined ratio to produce a horizontal timing signal HT with a horizontal scanning cycle. For example, according to an NTSC method, a base clock BCK having a frequency of 14.32 MHz, which is 4 times larger than a frequency of 3.58 MHz of a color subcarrier used in the signal processing, is divided into 1/910 to produce the horizontal timing signal HT. A vertical timing control circuit 3v which includes a counter for counting the horizontal timing signal HT divides the horizontal timing signal at a predetermined ratio to produce a vertical timing signal VT with a vertical scanning cycle. For example, according to the NTSC method, the vertical timing signal VT is produced by further dividing the horizontal timing signal HT, which is the base clock BCK with a frequency of 14.32 MHz divided by 910, by 2/525. Thus, respective timing of the horizontal and vertical scanning of the solid state image pickup device 1 are determined.
An analog signal processing circuit 4 captures the image signal Y0(t), which is output from the solid state image pickup device 1, and produces an image signal Y1(t) having a signal processed according to a predetermined format by performing processing such as sample-and-hold, holding and level-compensation. An A/D conversion circuit 5 captures the image signal Y1(t) and converts the analog value into digital data on a pixel-by-pixel basis to produce image data D0(n). A digital signal processing circuit 6 captures the image data D0(n) and performs processing such as color separation or color difference matrix and balance modulation to produce image data D1(n) including luminance data and color difference data. The image data D1(n) thus produced is sent to a display device such as a TV monitor, or is recorded on a recording medium such as a videodisc.
An exposure control circuit 7 produces a discharge-timing signal. The exposure control circuit 7 integrates the image data D0(n) output from the A/D conversion circuit 5 on a pixel-by-pixel basis and changes timing to produce a discharge timing signal DT according to the integrated value. In other words, this discharge timing signal DT is produced with delayed timing if the integrated value with respect to the image data D0(n) exceeds an appropriate range. The accumulation time L of the information charges is therefore made short. However, the discharge timing signal DT is produced with hastened timing if the integrated value does not reach the appropriate range, which extends the accumulation time L of the information charges. Accordingly, feedback is controlled to keep the solid state image pickup device 1 in an appropriate exposure condition.
Image scanners are now often used to scan a subject original when image data is input to computer equipment such as a personal computer or the like. Furthermore, use of an image pickup apparatus such as a video camera capable of taking a movie picture has also been considered. To connect the image pickup apparatus provided with a solid state image pickup device to the computer equipment, an expansion board, which is called a video capture board, is mounted on the computer equipment. An image signal being output from the image pickup apparatus is converted into a signal suitable for the computer equipment, thereby capturing the signal into a memory mounted on the computer equipment.
FIG. 3 is a block diagram showing the structure of a video capture board. A video capture board 10 comprises a frame memory 11, a synchronous detection circuit 12, a timing control circuit 13, and an interface circuit 14. The frame memory 11 stores image data D1(n), which is input from the image pickup apparatus on a screen-by-screen basis. A dual port type dynamic RAM is used as the frame memory 11 to simultaneously write and read the image data D1(n). The synchronous detection circuit 12 detects synchronous components contained in the image data D1(n), which is input from the image pickup apparatus, and produces a timing pulse according to timing of vertical and horizontal scanning. According to the timing pulse supplied from the synchronous detection circuit 12 and the instructions supplied from the personal computer, the timing control circuit 13 controls timing of writing and of reading the image data D1(n) to and from the frame memory 12. The image data D1(n) input from the image pickup apparatus on a screen-by-screen basis is stored in the frame memory 11 on a screen-by-screen basis, and it is also read on a screen-by-screen basis and transferred to the personal computer at the same time.
According to instructions from the timing control circuit 13, the interface circuit 14 reads the image data D1(n) stored in the frame memory 11 and transfers it to the personal computer. The interface circuit 14 sends interrupt instructions, which are output from the timing control circuit 13, to the personal computer and supplies the timing control circuit 13 with read-out instructions which are sent from the personal computer. Thus, the image data D1(n) to be stored in the frame memory 11 is transferred to the personal computer with desired timing.
In response to commands conforming to keyboard-entered commands or operation programming, the personal computer which captures image data from the video capture board 10 repeats time-sharing processing such as capturing of image data, performing various types of operations, accessing the built-in memory, and controlling the screen display. However, as it is difficult to capture image data successively at high speed, the processing may fall behind the operation of the image pickup apparatus. For example, image data of dozens of frames per second is captured from the image pickup apparatus according to a general television system such as an NTSC system or a PAL system, while a normal personal computer has a limited capacity of capturing image data of several frames per second. The video capture board 10 is configured to take a part of the image data by the write control of the frame memory 12 and to transfer the partial image data only to the personal computer.
Since such an image pickup system has an expensive video capture board 10 which requires a high-capacity frame memory 11, it is considered to activate the image pickup apparatus in accordance with the operation of the computer equipment. For example, according to the technology disclosed in Japanese Patent Laid-Open Publication No. Hei 7-87404, the computer equipment controls the timing of activating the vertical scanning and horizontal scanning of the image pickup device to take image data, which is obtained by the image pickup apparatus, directly into the computer equipment.
However, since the computer equipment must perform a number of processes in various ways in order to control the timing of the vertical and horizontal scans of the image pickup device, such processing becomes a large burden on the computer equipment. Therefore, the image data cannot be transferred from the image pickup device to the computer equipment at high speed.
Under such circumstances, it is an object of the present invention to reduce the cost of an image pickup system for capturing image information into computer equipment and to enable quick transfer of the image information to the computer equipment.
The invention has been designed to remedy the drawbacks described above. It is characterized by an image pickup i apparatus which takes pictures of an object and supplies computer equipment with image information on a screen-by-screen basis, comprising a solid state image pickup device on which a plurality of pixels are arranged in the form of a matrix and which stores information charges corresponding to the object image on the respective pixels; a vertical timing control circuit which determines repeatedly a vertical scanning period of the solid state image pickup device in a given period according to a reference clock with a given cycle; a horizontal timing control circuit which is synchronized with the reference clock and determines horizontal scanning timing of the solid state image pickup device in response to a transfer trigger supplied from the computer equipment; a drive circuit which discharges the information charges accumulated on the respective pixels of the solid state image pickup device and outputs to transfer sequentially on a line-by-line basis information charges newly stored after a lapse of a desired period upon being controlled by the vertical timing control circuit and the horizontal timing control circuit; and an exposure control circuit which determines a period between timing for discharging the information charges of the solid state image pickup device and timing for starting the information charge transferring output according to a level of the image signal. In this device, the exposure control circuit completes the discharge of the information charges of the solid state image pickup device within a retrace line period of the horizontal scanning determined by the horizontal timing control circuit.
Thus, since it becomes unnecessary to control the timing to start the vertical scanning of the solid state image pickup device from the computer equipment, a burden on the computer equipment is reduced. The electric charge is discharged by the exposure control within a horizontal blanking period, so that a noise due to the operation of discharging the information charge does not superpose on an effective period of the image signal.
The invention has a further feature in the vertical timing control circuit which includes a counter for counting the frequency of horizontal scanning of the solid state image pickup device for each vertical scanning period, and, when a count value of the counter does not reach a predetermined level on completion of the vertical scanning period, suspends the vertical scanning of the drive circuit, and fixes the control condition of the exposure control circuit.
Thus, if the number of horizontal scanning falls short within a predetermined vertical scanning period, i.e., if all information charges cannot be read thoroughly, the vertical scanning period is temporarily doubled, and the information charges are continuously read. Therefore, even if the operation of reading the information charges is delayed, all the information charges on one image plane can be read without fail.